FUNCTIONAL STRUCTURE FOR CORRECTING INTERMEDIATE SUM ±[Si] ARGUMENTS FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-) Russian patent published in 2010 - IPC G06F7/50

Abstract RU 2378681 C2

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations of summation and subtraction in position-sign codes. Each bit of the adder is made in form of two channels of equivalent structure - positive and conditionally negative. In on version of implementation, the i^th bit of each channel contains four AND logic components and two NOR logic components.

EFFECT: simplification of the functional structure of the adder.

4 cl, 21 dwg

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RU 2 378 681 C2

Authors

Petrenko Lev Petrovich

Dates

2010-01-10—Published

2007-12-17—Filed