FUNCTIONAL STRUCTURE OF PARALLEL ADDER FOR MULTIPLICATION, WHEREIN ARGUMENTS OFTERMS OF PARTIAL PRODUCTS ARE ARGUMENTS OF TERNARY NUMBER SYSTEM f(+1,0,-1) IN POSITIONAL-SIGN FORMAT THEREOF f(+/-) (VERSIONS) Russian patent published in 2010 - IPC G06F7/505

Abstract RU 2386162 C2

FIELD: physics.

SUBSTANCE: in the first version each bit of the adder is in form of positive and conditionally negative summation channels, each of which has two NAND logical elements, AND logical element and two OR logical elements.

EFFECT: increased operation speed of the device.

2 cl, 11 dwg

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RU 2 386 162 C2

Authors

Petrenko Lev Petrovich

Dates

2010-04-10—Published

2008-04-29—Filed