FUNCTIONAL STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICANT [m]f(2) AND MULTIPLIER [n]f(2) WITH MINIMISED PROCEDURE OF FORMING FIRST LEVEL INTERMEDIATE SUMS f[S] OF PARTIAL PRODUCTS, WHERE k IS NUMBER OF FIRST LEVEL INTERMEDIAT SUMS (VERSIONS) Russian patent published in 2011 - IPC G06F7/527

Abstract RU 2422880 C1

FIELD: information technology.

SUBSTANCE: in the first version, the multiplier design has four adders, linear logic functions AND, as well as three linear logic functions OR for generating intermediate sums of partial products of the first level of summation, wherein functional structure of the adders is adapted to receive position-sign arguments of intermediate sums of partial products.

EFFECT: simple functional structure of a parallel-serial multiplier and high speed of operation of the multiplier.

4 cl

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RU 2 422 880 C1

Authors

Petrenko Lev Petrovich

Dates

2011-06-27—Published

2010-03-22—Filed