FUNCTIONAL OUTPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) (VERSIONS) Russian patent published in 2011 - IPC G06F7/527

Abstract RU 2422881 C1

FIELD: information technology.

SUBSTANCE: in one version, the device has two logic structures, each consisting of j AND logic elements, a logic structure consisting of j+2 AND logic elements and a logic structure consisting of j+2 OR logic elements.

EFFECT: simple design of the multiplier and high speed of operation.

4 cl

Similar patents RU2422881C1

Title	Year	Author	Number
FUNCTIONAL STRUCTURE OF PARALLEL-SERIES MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2)	2010	Petrenko Lev Petrovich	RU2439660C2
FUNCTIONAL STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICANT [m]f(2) AND MULTIPLIER [n]f(2) WITH MINIMISED PROCEDURE OF FORMING FIRST LEVEL INTERMEDIATE SUMS f[S] OF PARTIAL PRODUCTS, WHERE k IS NUMBER OF FIRST LEVEL INTERMEDIAT SUMS (VERSIONS)	2010	Petrenko Lev Petrovich	RU2422880C1
METHOD OF PARALLEL-SERIAL MULTIPLICATION OF POSITIONAL ARGUMENTS OF ANALOGUE SIGNALS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2)	2010	Petrenko Lev Petrovich	RU2437142C2
FUNCTIONAL STRUCTURE FOR PRE-ADDER OF PARALLEL-SERIAL MULTIPLIER f(Σ) WITH MULTIPLICAND ARGUMENTS [m]f(2) AND MULTIPLIER ARGUMENTS [n]f(2) IN POSITION FORMAT (VERSIONS)	2010	Petrenko Lev Petrovich	RU2422879C1
FUNCTIONAL STRUCTURES FOR PARALLEL-SERIAL RIPPLE CARRY f(←←)и f(←←) IN CONDITIONAL "i" "FORMATION ZONE" FOR CORRECTING RESULTANT PRELIMINARY FIRST LEVEL SUM OF ARGUMENTS OF PARTIAL PRODUCTS OF PARALLEL-SERIAL MULTIPLIER f(Σ) OF POSITIONAL FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) (VERSIONS)	2010	Petrenko Lev Petrovich	RU2431886C1
FUNCTIONAL STRUCTURE OF PRE-ADDER f(Σ) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER f(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [Sj]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS)	2011	Petrenko Lev Petrovich	RU2586565C2
METHOD TO GENERATE ARGUMENTS OF ANALOG SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) ARGUMENTS OF MULTIPLICAND [m]f(2) AND ARGUMENTS OF MULTIPLIER [n]f(2) - "ADDITIONAL CODE" IN PYRAMIDAL MULTIPLIER f(↓Σ) FOR SUBSEQUENT LOGICAL DECODING f(CD↓) AND GENERATION OF RESULTING SUM IN FORMAT [S]f(2) -"ADDITIONAL CODE" AND FUNCTIONAL STRUCTURE FOR ITS REALISATION (VERSIONS OF RUSSIAN LOGICS)	2011	Petrenko Lev Petrovich	RU2481614C2
METHOD OF GENERATING ORDERED SEQUENCES OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [n]f(2) AND [m]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(↓Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)	2011	Petrenko Lev Petrovich	RU2463645C1
METHOD OF GENERATING ARGUMENTS OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [m]f(2) И [n]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)	2011	Petrenko Lev Petrovich	RU2473955C1
FUNCTIONAL STRUCTURE OF SELECTIVE LOGICAL DIFFERENTIATION OF ARGUMENTS OF BINARY SYSTEM FORMAT f(2)	2008	Petrenko Lev Petrovich	RU2373640C1

RU 2 422 881 C1

Authors

Petrenko Lev Petrovich

Dates

2011-06-27—Published

2010-03-04—Filed