SYSTEM AND METHOD FOR LOW-POWER LOGIC FOR NUMBER BUS IN MEMORY Russian patent published in 2011 - IPC G11C8/08 

FIELD: information technology.

SUBSTANCE: electronic device for saving power in a memory device has memory comprising a plurality of number buses. The memory includes a plurality of memory banks, wherein each of the plurality of memory banks includes a pair of sub-banks, each pair of sub-banks sharing pre-decoded data. The electronic device also includes a plurality of number bus generators connected to memory, wherein each number bus generator is associated with the number bus from the plurality of number buses of the memory. Power in each of the plurality of number bus generators is switched off in the default state except during the period for accessing the number bus. The electronic device also includes a decoder which is connected to the plurality of number bus generators in order to receive a request for accessing memory, and in order to decode the request for accessing memory in order to determine the address associated with the request for accessing memory. The decoder records the selected number bus generator but not other number bus generators from the plurality of number bus generators, in response to the request for accessing memory.

EFFECT: reduced current leakage in memory devices.

11 cl, 9 dwg, 3 tbl