FIELD: information technology.
SUBSTANCE: memory device contains the first column of memory cells which includes the first memory cell; the second column of memory cells which includes the second memory cell; the fist bit line connected with the first column of memory cells; the second bit line connected with the second column of memory cells; and source line shared by the first column of memory cells and the second column of memory cells. In this device, while the first memory cell is being read the first bit line carries the first voltage, the second bit line carries the second voltage and source line carries the third voltage, where the second and the third voltage are essentially the same.
EFFECT: decrease of device area, increase of matrix density and simplification of source line routing due to reduced number of source lines.
20 cl, 5 dwg
