FIELD: electricity.
SUBSTANCE: implemented display device contains a panel with an active matrix, the first drive circuit of scanning signal lines and the second drive circuit of scanning signal lines. The first and the second circuit contain the first and the second shift registers respectively. The shift registers contain cascades. Each cascade of the first and the second shift registers displays scanning pulse (Qn-1) by way of transfer of the clock pulse of the synchronisation signal set through the first input contact terminal of synchronisation signal. The first transistor (Tr2) is provided to connect/disconnect the scanning signals line corresponding to a separate cascade to/from the power supply source with a low level of scanning pulse strength; the first transistor has a gate receiving the synchronisation signal set through the second input contact terminal of synchronisation signal. The two synchronisation signals set to the first shift register and the two synchronisation signals set to the second shift register differ from each other by their clock pulses time distribution.
EFFECT: limitation of transistor threshold voltage shift generation combined with gate line voltage dump.
18 cl, 14 dwg
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Authors
Dates
2012-05-27—Published
2008-10-20—Filed