INTERFACE LOGIC FOR MULTI-CORE SYSTEM-ON-A-CHIP (SoC) Russian patent published in 2012 - IPC G06F13/00 

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to multi-core system-on-chip (SoC). The power consumption control device includes: a system-on-chip comprising: a first core and a second core; interface logic connected to the first core and the second core, the interface logic including a firewall logic, a bus logic, and a test logic; a chipset logic connected to the interface logic and including a memory controller to enable data communication with a memory connected to the SoC; and a virtual firewall logic connected between the chipset logic and the second core, wherein the second core can be disabled during normal operation to provide for a single core SoC.

EFFECT: low power consumption of the SoC by disabling the second core during normal operation to provide for a single core SoC.

20 cl, 5 dwg