PARTIAL WIDTH LOADING DEPENDING ON REGIME, IN PROCESSORS WITH REGISTERS WITH LARGE NUMBER OF DISCHARGES, METHODS AND SYSTEMS Russian patent published in 2017 - IPC G06F9/30 

FIELD: information technology.

SUBSTANCE: processor for loading data contains a register which has a width; a decoding unit for receiving a partial width loading instruction. The partial width loading instruction indicates the memory location as the source operand and indicates the register as the destination operand; a memory subsystem connected to the decoding unit. The memory subsystem is designed to load data from a specified memory location to the processor, in response to a partial width loading instruction; and a register writting unit connected to the memory subsystem and the register. The register writing unit is designed, in response to the partial width loading instruction, for writing at least a portion of the downloaded data on the partial width of the register and for completing writing to the register with a set of digits stored on the remaining width of the register which have bit digits which depend on the regime of loading the processor's partial width. The partial width loading instruction does not indicate the partial width loading regime.

EFFECT: improving the performance of processor systems by using several regimes to process the loading instruction of the partial width and its operation code.

25 cl, 17 dwg