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2 476 922

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C1

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IPC

G06F7/505(2006-01-01)

(21) (22)

Application

2012104961/08, 2012-02-13

(24)

Start date

2012-02-13

(22)

Actual filing date

2012-02-13

(45)

Published

2013-02-27

(72)

Inventor

Petrenko Lev Petrovich

(73)

Holder

Petrenko Lev Petrovich

FUNCTIONAL DESIGN OF ADDER f(Σ) OF "k" CONDITIONALLY MOST SIGNIFICANT BITS OF PARALLEL-SERIAL MULTIPLIER f(Σ), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF TERMS [S ] AND [S ] "COMPLEMENTARY CODE RU" BY ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d/dn → f(←↓) (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2013 - IPC G06F7/505

Abstract RU 2476922 C1

FIELD: information technology.

SUBSTANCE: one version, the functional design is realised using logic elements AND, OR.

EFFECT: faster operation.

2 cl

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RU 2 476 922 C1

Authors

Petrenko Lev Petrovich

Dates

2013-02-27—Published

2012-02-13—Filed