VOLTAGE DEBOOSTER WITH NEGATIVE DYNAMIC RESISTANCE SECTION Russian patent published in 2013 - IPC H01L29/86 

FIELD: electrical engineering.

SUBSTANCE: voltage debooster with a negative dynamic resistance section containing a multilayered silicon structure the layers whereof form serially positioned p-n junctions and contacts; the structure contains at least five layers wherein the carrier lifetime is equal to a value from the interval τ=0.01-1 mcsec; the alloying admixture concentration in the layers is within the interval of 1·10¹⁵-1·10²⁰ cm^-3; the layers are designed for the condition h_i>√D_iτ_i to be true for at least one layer where h_i is the specified layer thickness, D_i is the coefficient of carrier diffusion in the layer, τ_i is the carrier lifetime in the layer, with the condition h_j<√D_jτ_j true for at least one layer of the structure where h_j is the specified layer thickness, D_j is the coefficient of carrier diffusion in the layer, τ_j is the carrier lifetime in the layer.

EFFECT: creation of a voltage debooster with a negative dynamic resistance section; increase of the maximum allowable dissipation power at the debooster fixed voltage.

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