MANUFACTURING METHOD OF VERTICAL LOW-VOLTAGE VOLTAGE LIMITER Russian patent published in 2019 - IPC H01L21/18 

FIELD: electrical engineering.

SUBSTANCE: invention relates to semiconductor electronics and can be used for making discrete voltage limiters. Method of producing a vertical low-voltage voltage limiter includes forming on a high-alloy substrate a first type of conductivity of local areas of a latent layer of a second conductivity type, deposition of a low-alloy epitaxial layer of a second conductivity type, formation of areas of the device with the help of slot insulation, formation of high-alloy areas of the first and second conductivity types on the low-alloyed surface. Formation of local areas of hidden layer is carried out by deposition of high-doped epitaxial layer of second conductivity type with subsequent local etching of epitaxial layer to high-doped substrate of first conductivity type, wherein thickness of high-alloy epitaxial layer is not more than 1 mcm. Invention ensures production of low-voltage low-capacitance voltage limiters with low leakage currents due to high crystalline perfection of the formed high-alloy layer and minimized thermal treatment of junctions.

EFFECT: method differs by simplicity in comparison with traditional methods for production of hidden layers by diffusion and impurity implantation and allows reducing cost of device manufacturing.

1 cl, 6 dwg