METHOD OF MAKING SELF-ALIGNED HIGH-VOLTAGE INTEGRATED TRANSISTOR Russian patent published in 2013 - IPC H01L21/328 

FIELD: physics.

SUBSTANCE: in a self-aligned, high-voltage transistor, p-n junctions are formed within a semiconductor substrate without coming out on to the surface, and contacts to regions of the transistor are insulated in the vertical portion by separating dielectrics from the regions of the transistor which bring the bottom portion into contact with the latter. The high-voltage integrated transistor is insulated from the substrate by a dielectric layer. Self-alignment in the structure is achieved using a screening layer over the contact to the collector region while forming slits under the contact to the collector region and the insulating region and screening layers over contacts to the emitter region while forming slits under contacts to the base region and emitter region.

EFFECT: high breakdown voltage of p-n junctions of an integrated transistor, high packing density of transistor structures and faster operation thereof.

3 cl, 10 dwg