METHOD OF MANUFACTURE OF PLANAR LARGE AREA pin PHOTO DIODES ON HIGH-RESISTANCE p-SILICONE Russian patent published in 2015 - IPC H01L31/18 H01L21/265 

FIELD: physics.

SUBSTANCE: offered invention relates to technology of manufacture of semiconductor devices, in particular, to methods of manufacture of planar large area pin-photo diodes based on high-resistance silicon of p-type conductivity. The method includes preparation of a plate of source p-silicon or silicon epitaxial structure of p⁺-p-type, formation of a mask for implantation of P⁺ ions into a working area and a security ring, two-phase implantation of P⁺ ions with the energy and the dose respectively (30÷40) keV and (3÷4)·10¹⁵ cm^-2 on the first and (70÷100) keV and (8÷10)·10¹⁵ cm^-2 at the second stage for formation of n⁺-p transitions of working area and the security ring, implantation of $$B{F}_{+}^2$$ ions with the energy (60÷100) keV and the dose (2÷3)·10 cm^-2 from the back side of the plate, two-phase post-implantation annealing at duration and temperature respectively no less than 1 hour and (570÷600)°C on the first stage and no less than 5 hours and (890÷900)°C at the second stage, protection and an enlightenment of a surface of working area and protection of the periphery of the security ring by application of SiO₂ film, and annealing, initial decrease of temperature after annealing up to 300°C and application of SiO₂ film at the temperatures over 300°C is made in the conditions of oxygen lack, and implantation P⁺ and $$B{F}_{+}^2$$ ions is performed one after another in any sequence.

EFFECT: optimum selected implantation doses, modes and conditions of post-implantation annealing and conditions of application of protective and lightening coating provide increase of current sensitivity of pin-photo diodes at high background flares with preservation of low level of dark currents at decrease of complexity, labour input and energy consumption of manufacture.

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