FIELD: physics, computer engineering.
SUBSTANCE: invention relates to computer facilities, it is intended for summation of binary numbers and can be used in information processing and transmission systems for digital signal processing, at resolution of combinatory tasks. The device contains treelike structure of adders, OR element and a comparator, the information data inputs of the multiinput adder are combined in M groups of n-digit external inputs of the device, (M-1) n-digit adders of treelike structure are combined in k cascades (k=]log2M[grater integer), the first cascade contains [M/2] (the whole part) of adders, the second cascade contains [M/4] adders, …, ith cascade contains [M/2i] adders (i=3, 4, …, k-1), …, kth cascade contains one adder, signals of cascades adders transfers and the comparator output which compares the calculated sum of the array of input data with the pre-set threshold, combines by OR and forms an output signal of threshold excess.
EFFECT: minimising of hardware costs and expansion of functionality due to summation of data files and control of total sum of data with the pre-set threshold.
1 dwg
Authors
Dates
2015-04-10—Published
2013-06-28—Filed