FIELD: computer equipment.
SUBSTANCE: device comprises M digits D1, …, DM of a set of input data from N a bit binary number consisting of L sets of M bits in a set, where N=L*M, N external outputs of bit groups QG1, …, QGN, group of external outputs of total number of groups QK, external output of left (first) QLB bit, group of external outputs of number of single bits QU, group of external outputs of number of zero bits QZ, module FK of detection of groups 1, first trigger of TEB of reception permission 2, flip-flop TLB of left (first) bit 3, "XOR" element 4, an AND element with one inverse input 5, a first group shift 6 unit SF_1, a first adder SM_G bits in group 7, subtractor SB 8, a second group shift 9 unit SF_2, a second adder SM_K of the number of groups 10, a third adder SM_U of the number of single bits 11, a starting-stopping trigger TPO 12, RG_G register of groups of bits 13, register RG_K of number of groups 14, register RG_U of number of single bits 15, third module SF_3 of shift of groups 16, fourth adder SM_N of complement 17, fifth adder SM_Z of number of zero bits 18, second trigger TEQ of reception permission 19, first output buffer register of groups 20, second output buffer register of total number of groups 21, output trigger of left (first) bit of input data 22, a third output buffer register for the number of single bits 23, a fourth output buffer register of the number of zero bits 24, external inputs C of clock signals 25, R of synchronous setting to zero state 26, start of START, STOP stopping and an internal decrementation flag FD.
EFFECT: technical result consists in enabling detection of groups of single and zero bits in binary numbers, as well as simple increase in the input information width while reducing hardware costs.
1 cl, 3 tbl, 2 dwg
