METHOD OF MANUFACTURING INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES Russian patent published in 2016 - IPC H01L21/60 B82B3/00 

FIELD: technological processes.

SUBSTANCE: invention can be used for manufacturing of multilevel system of silicon integrated circuit interconnections. Invention comprises forming cavities for future interconnection conductors in the insulating layer of silicon structure in which there are semiconductor devices, forming nanosized particles, growing nanomaterial on said nanosized particles, filling the remained cavities space with conductive material, forming composite material of nanomaterial and conducting material, planarizing surface of the silicon structure preserving applied materials in cavities, before forming nanosized particles alloy are applied on the bottom and walls of the cavities layer, alloy contains a component for forming nanosized particles, which is an element or a combination of elements of I and/or VIII group, and a component for forming diffusion barrier layer, which is a transition metal or a combination of transition metals of IV-VI groups of the Element periodic table, and thermal action on it.

EFFECT: simplifying technology of forming, increasing resistance and thermal stability of interconnections at high current density.

7 cl, 10 dwg