FIELD: physics.
SUBSTANCE: device comprises a cell memory matrix with banks, wherein each bank includes rows, the first word lines provided in accordance with the rows, an address latch-circuit, which latches the first row address signal, a row decoder, which activates one of the first word lines, and a control circuit, that is configured to perform the first operation, which activates one of the banks on the basis of the bank address signal, when the first instruction is loaded, and the second operation, which latches the first row address signal in the address latch-circuit and to perform the third operation, which activates one of the first word lines by the row decoder on the basis of the second row address and the first row address signal latched in the address latch-circuit, when the second instruction is loaded after the first instruction.
EFFECT: increasing the number of the address bits with the unchanged device specifications.
35 cl, 21 dwg
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