FIELD: physics.
SUBSTANCE: device contains memory blocks, each of which includes an array of memory cells; word lines connected to the lines of each of the memory blocks; an address latch-circuit configured to capture a complete address for determining one of the word lines, wherein the full address includes the first address and the second address; and a control circuit configured to ignore the reset operation for the first address as the target of the setup operation and to rewrite the first address in accordance with the setup operation upon receiving the first instruction for determining the reset operation for the storage unit and the setting operation for the first address.
EFFECT: implementing a memory device that is capable of high-speed operation and has a large capacity.
14 cl, 10 dwg
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Authors
Dates
2017-10-24—Published
2014-07-29—Filed