FIELD: electricity.
SUBSTANCE: front surface of the solid state power transistor is settled out by the silicium nitride from a gaseous phase 0.1-0.2 microns thick in the solid state power transistor manufacturing process. The polycrystalline silicon in the grooves is acidulated after the impurity doping process under a pressure of not less than 1 MPa and at a temperature of not above 850°C over a period of 5-20 min and after that the silicium nitride is removed by etching in orthophosphoric acid or by selective plasma-chemical etching.
EFFECT: manufacturing route standardisation by using self-alignment and cross-alignment methods in photolithography processes, which leads to the equipment accuracy reduction and the staff competence in critical activities requirements, resulting in reduced labour costs for the products manufacture and in a higher yield value.
8 dwg
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Authors
Dates
2017-06-29—Published
2016-07-06—Filed