PAIRS OF INSTRUCTIONS ESTABLISHING EXECUTION ORDER OF INSTRUCTIONS, PROCESSORS, METHODS AND SYSTEMS Russian patent published in 2017 - IPC G06F9/38 

Abstract RU 2630745 C2

FIELD: information technology.

SUBSTANCE: processor contains an instruction fetch block for retrieving a pair of instruction establishing the execution order of instructions, which should be part of the instruction set of the processor. The pair of instructions establishing the execution order of instructions includes an activation instruction and an establishment instruction. The activation instruction appears before the establishment instruction in the program queue; and a queue sequencer in response to the pair of instruction establishing the execution order of instructions, to prevent the processing of instructions that appear after the instruction in the program queue, before the activation instruction in part, with a change in the execution order of the processor instructions.

EFFECT: ensuring the desired execution order of instructions.

24 cl, 20 dwg

Similar patents RU2630745C2

Title Year Author Number
INSTRUCTION AND LOGIC FOR IDENTIFICATION OF INSTRUCTIONS FOR REMOVAL IN MULTI-FLOW PROCESSOR WITH SEQUENCE CHANGING 2013
  • Kozarev Nikolaj
  • Shishlov Sergej I.
  • Ier Dzhajesh
  • Butuzov Aleksandr
  • Babayan Boris A.
  • Kluchnikov Andrej
RU2644528C2
PARTIAL WIDTH LOADING DEPENDING ON REGIME, IN PROCESSORS WITH REGISTERS WITH LARGE NUMBER OF DISCHARGES, METHODS AND SYSTEMS 2014
  • Rash Uilyam K.
  • Santiago Yazmin A.
  • Dikson Martin Gaj
RU2638641C2
INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE 2013
  • Leshenko Anton U.
  • Efimov Andrej
  • Shishlov Sergej I.
  • Ier Dzhajesh
  • Babayan Boris A.
RU2662394C2
PROCESSORS, METHODS, SYSTEMS AND INSTRUCTIONS FOR TRANSCODING POINTS OF UNICODE VARIABLE LENGTH CODE 2014
  • Ko Shitszon
RU2638766C2
INSTRUCTION AND LOGICAL SCHEME FOR SORTING AND LOADING OF SAVE INSTRUCTIONS 2014
  • Lechenko, Anton
  • Efimov, Andrey
  • Shishlov, Sergey Y
  • Kluchnikov, Andrey
  • Garifullin, Kamil
  • Burovenko, Igor
  • Babayan, Boris A.
RU2663362C1
COMPLETION OF INSTRUCTION WITH ACCOUNT OF CONSUMED ENERGY 2009
  • Sperber Zeev
  • Marom Rafi
  • Levi Ofer
RU2427883C2
METHOD AND DEVICE FOR EXECUTING PROCESSOR INSTRUCTIONS BASED ON DYNAMICALLY VARIABLE DELAY 2007
  • Michalak Dzherald Pol
  • Dokser Kennet Alan
RU2419836C2
INSTRUCTION AND LOGICAL CIRCUIT TO CARRY OUT DOT PRODUCT OPERATION 2007
  • Zokhar Ronen
  • Sekoni Mark
  • Partkhasaratkhi Radzhesh
  • Chennupati Srinivas
  • Bakston Mark
  • Desil'Va Chak
  • Abdallakh Mokhammad A.
RU2421796C2
MODULE FOR COPROCESSOR CACHE 2011
  • Dzhkha Ashish
RU2586589C2
PROCESSOR, METHOD, SYSTEM AND EQUIPMENT FOR VECTOR INDEXED MEMORY ACCESS PLUS ARITHMETIC AND / OR LOGIC OPERATIONS 2014
  • Ermolaev Igor
  • Toll Bret L.
  • Velentajn Robert
  • San Adrian Khesus K.
  • Doshi Gautam B.
  • Chakraborti Prasendzhit
  • Malladi Rama K
RU2620930C1

RU 2 630 745 C2

Authors

Dikson Martin Dzh.

Rash Uilyam K.

Santiago Yazmin A.

Dates

2017-09-12Published

2014-06-12Filed