FIELD: instrument making.
SUBSTANCE: use: for the discrete instruments and microwave (SHF) integrated circuits development. Essence of the invention consists in the fact, that the field effect transistor with the additional field electrode manufacturing method comprises the active region isolation by chemical, physical etching or implantation, the ohmic drain and source terminals creation on the contact layer surface, or the semiconductor structure penetration into the contact layer, the contact layer selective etching, the Schottky gate formation on the barrier layer, or isolated from the gate the additional gate electrode penetration into the barrier layer, with the purpose of generated by the L-shaped gate cap edges stray capacitances reduction, the frequency range increasing, simultaneous increase in the breakdown voltages, the drain-source channel operating temperature reduction, pinch-off voltage reduction, increase in the steepness gm maximum value and increase in the power gain, as well as increase in the of suitable transistors yield instead of strip or T-shaped gates, the Schottky L-shaped gate is used, which L-shaped cap formation occurs at the dielectric film edge or at the metal film edge, or at the combined film edge with their possible subsequent removal from the L-gate cap edge, the protective dielectric application with the air or other cavities formation under the L-gate cap edge, which leads to the stray capacitance reduction between the L-gate cap and the contact layer surface, electrically isolated from the gate field electrode is formed in the drain-source channel; the field electrode electrical connection to the source is implemented either by lying on the dielectric narrow bridges, either, in order to reduce the stray capacitance, by narrow or continuous along the gate entire width air bridges.
EFFECT: technical result is enabling the stray capacitances reduction possibility, increase in the frequency range, increase in the breakdown voltages, the drain-source channel operating temperature reduction, pinch-off voltage reduction, increase in the steepness maximum value and increase in the power gain, as well as increase in the suitable transistors yield.
1 cl, 3 dwg
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Authors
Dates
2018-10-30—Published
2016-01-26—Filed