FIELD: digital information processing systems.
SUBSTANCE: in a self-timed single-bit ternary adder containing two AND-OR-NOT elements, two OR-AND-NOT elements, three OR-NOT elements, a disparity element with two paraphase inputs and one paraphase output, two AND-NOT elements, two hysteresis triggers, an inverter and the corresponding components of the first and second terms, the first and second paraphase transfer inputs, the first and second paraphase transfer outputs, the ternary sum output, and an indicator output, the second disparity element, the third, fourth and fifth AND-NO elements, two OR elements and a generator of the zero and inverse zero components of the sum output and the indicator output of the adder are introduced.
EFFECT: providing a self-timed implementation of a single-bit quaternary adder with a single add spacer.
4 cl, 4 dwg, 4 tbl
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