FIELD: programmable logic devices.
SUBSTANCE: user programmable gate array (FPGA) configured to implement a logic function, wherein the FPGA comprises a plurality of hardware search tables (LUT), wherein the selection lines or outputs of each LUT are programmable in a mutually connected manner to selection or output lines of another LUT through a plurality of programmable switches, multiple flip-flops in the shift register configuration, wherein each LUT has at least one input connected to the corresponding flip-flop output, and each programmable switch is connected to the additional corresponding trigger output; wherein FPGA is configured to operate in first mode, in which shift register is loaded with predetermined test values, and in second mode, in which shift register is loaded with values realizing said logic function.
EFFECT: technical result is reduced space of chip allocated for addressing of cells of storage devices, improved testing.
15 cl, 13 dwg
