DEGENERATIVE-TYPE VOLTAGE STABILIZER ON FIELD-EFFECT TRANSISTORS FOR OPERATION AT LOW TEMPERATURES Russian patent published in 2020 - IPC G05F1/56 H03F3/45 

FIELD: electricity.

SUBSTANCE: invention relates to secondary power sources and can be used in the structure of analogue and digital microcircuits operating in cryogenic temperatures and radiation effects. To achieve technical result, degenerative-type voltage stabilizer (DVS) for field-effect transistors for operation at low temperatures comprises control element (1) on field-effect transistor, drain of which is connected to source of supply voltage (2), and source is connected to device output (3), mismatch signal differential amplifier (4) with inverting (5) and non-inverting (6) inputs, first current output (7), as well as current input (8), establishing static mode of differential error signal amplifier (4), connected to common bus of power supply (9) through reference current source (10), reference voltage source (11) connected to non-inverting input (6) of differential error signal amplifier (4), wherein output of device (3) is connected to inverting input (5) of differential error signal amplifier (4). First (7) current output of mismatch signal amplifier (4) is connected to gate of first (12) additional field-effect transistor, and also connected to source of first (12) additional field transistor and to gate of field transistor of control element (1) through first (13) additional resistor, reference current source (10) is made on the basis of second (14) and third (15) additional field transistors, the drains of which are connected to current input (8) of the differential error signal amplifier (4), gates of second (14) and third (15) additional field-effect transistors are connected to common bus of power supply (9), source of second (14) additional field-effect transistor is connected to common bus of power supply (9) through second (16) additional resistor, and third (15) additional field-effect transistor source is connected to the power supply common bus (9) through third (17) additional resistor, wherein drain of first (12) additional field transistor is connected to first bias voltage source (18), and output of device (3) is connected to inverting input (5) of differential error signal amplifier (4) through resistive voltage divider (19), which comprises series-connected first (20) and second (21) resistors.

EFFECT: technical result of the claimed invention consists in creation of conditions in the architecture of the known DVS, at which it becomes possible to use JFET transistors and, as a result, reliable operation of the device in heavy operating conditions; besides, created by JFET DVS will have one more additional positive quality - voltage at gate of its JFET control element with n-channel will be less than output voltage of DVS; this significantly simplifies JFET control circuit with control element and creates optimum conditions for potential matching in DVS circuit, when maximum voltages on all other active elements of DVS are less than its output voltage.

7 cl, 12 dwg