LOW-TEMPERATURE AND RADIATION-PROOF COMPENSATION VOLTAGE STABILIZER ON COMPLEMENTARY FIELD TRANSISTORS WITH CONTROL P-N JUNCTION Russian patent published in 2020 - IPC H03F3/45 G05F1/56 

FIELD: physics.

SUBSTANCE: invention relates to secondary power sources and can be used in the structure of analogue and digital microcircuits operating in cryogenic temperatures and radiation effects. Technical result of the claimed invention is creation of conditions in the architecture of the known degenerative voltage stabilizer (DVS) on the CMOS field transistors at which it becomes possible to use JFET transistors and, as a result, reliable operation of the device in heavy operating conditions. Besides, created JFET DVS will have one more additional positive quality - voltage on gate of its JFET control element with n-channel will be less than output voltage of DVS. Technical result of claimed invention is achieved due to that low-temperature and radiation-stable compensation voltage stabilizer on complementary field transistors with control pn junction (Fig. 2) comprises first (1) power supply bus, output of device (2), output field transistor (3) of control element, source of which is connected to device output (2), and drain is connected to first (1) power supply bus, differential error signal amplifier (4) with first (5) and second (6) current outputs and common source circuit (7), second (8) power supply bus, current mirror (9), input of which is connected to first (5) current output of the differential error signal amplifier (4), inverting output is connected to second (6) current output of the differential error signal amplifier (4), wherein current mirror (9) has non-inverting output (10), resistive voltage divider (11), which input is connected to device (2) output, and output is connected to inverting differential signal amplifier (4) inverting input (12), reference voltage source (13) connected to non-inverting input (14) of differential error signal amplifier (4). Circuit includes first (15) additional field-effect transistor, drain of which is connected to second (8) power supply bus, gate is connected to second (6) current output of differential error signal amplifier (4), and source is connected to gate of output field transistor (3) of control element and is connected to device (2) output through additional resistor (16), wherein all said field transistors used are field-effect transistors with p-n control junction.

EFFECT: invention significantly simplifies control circuit of JFET control element and creates optimum conditions for potential matching in degenerative voltage stabilizer scheme, when maximum voltages on all other active elements of DVS are less than its output voltage; and this is impossible in CMOS DVS.

8 cl, 14 dwg