FIELD: computer engineering.
SUBSTANCE: device comprises an external ID data input, a group of external inputs of an IS pattern and inputs IK for setting the capacity of the input IS pattern, a group of external QB data outputs, the number of overlapping QS patterns, the number of non-overlapping QN patterns, and also contains the first RS-trigger of start-stop TSS 1, second delay trigger TZ 2, first OR element 3, first AND element 4, first counter of the number of overlapping patterns CTS 5, second counter of the number of non-overlapping patterns CTN 6, second AND element 7, second OR element 8, third subtracting counter of digits of template STK 9, fourth counter of intervals CTI 10, output buffer OB 11, first bit shift register of intervals RI 12, third trigger of the first bit of interval TRI 13, first group of elements AND with inverse input 141, 142,…, 14K, third OR element 15, second 161, 162,…, 16K and third 171, 172,…, 17K groups of AND elements, second input data shift register RD 18, group of OR elements 191, 192,… 19(K-1), decoder DC 20, comparator COMP 21, as well as external inputs of clock signal IC, device start START, device stop STOP and internal bits decoding buses BDC, a first comparator BA, a second comparator BB and an interval bit BU, internal flags of patterns resolution FE, equality FEQ, counter load FL, non-overlapping patterns FN, overlapping patterns FS, first counter state FS1 and unit interval FU, external exchange control bus EO, external flags “Buffer full” FF and “Buffer empty” FZ.
EFFECT: wider range of tools for the same purpose, particularly the possibility of detecting and separating overlapping and non-overlapping patterns of a given bit depth.
1 cl, 3 dwg
