FIELD: information technologies.
SUBSTANCE: invention relates to a device for detecting overlapping and non-overlapping bit patterns in a binary sequence. The device contains an ID data input, a group of external inputs of the IS pattern and setting the width of the input pattern IK, a group of external data outputs QB, a number of overlapping patterns QS and a number of non-overlapping patterns QN, and also contains a first RS start-stop trigger TSS 1, a second delay trigger TZ 2, first bit counter STV 3, output buffer OB 4, first AND element with inverse input 5, first OR element 6, third write trigger TW 7, second OR element 8, second subtractive bit counter of the STC template 9, second AND element 10, third element AND 11, third counter for the number of overlapping patterns CTS 12, fourth counter for the number of non-overlapping patterns CTN 13, input data shift register RD 14, decoder DC 15, group of (K-1) elements OR 161, 162, …, 16(K-1), the first group of K elements AND 171, 172, …, 17K, second group of K elements AND 181, 182, …18K and comparator COMP 19, as well as external inputs of clock signal IC, start device START, stop device STOP and internal buses of decryption of digits BDC, first comparison operand BA and second comparison operand BB, internal equality flags FEQ, loading of counter STC FL, non-overlapping patterns FN, resolution of FS patterns, first state of the counter STC FS1, start delay FZS and recording FW, external exchange control bus EO, external flag “Buffer full” FF and flag “Buffer empty” FZ.
EFFECT: possibility of detecting overlapping and non-overlapping patterns in the input data sequence.
1 cl, 3 dwg
