METHOD FOR TESTING A SERIAL BUS INTERFACE BASED ON INTRODUCTION OF CLOCK SIGNAL ERRORS Russian patent published in 2022 - IPC G06F11/08 G06F11/263 H04B3/46 

FIELD: testing.

SUBSTANCE: invention relates to a method for testing a serial bus interface based on introduction of clock signal errors. In the method, a first message is generated; then a second message is generated based on the first message, wherein the clock signal is replaced with a clock signal containing errors; the clock signal errors are formed from any combination of six half-bits with "0" or "1" values, wherein the number of clock signals with errors is not limited and is determined by the goals and strategy of testing; the generated messages are sent to the tested module (TM) three times according to the following algorithm: first time – the first message without errors; second time – the second message with the generated clock errors; third time – repeated first message without errors; then the condition of the TM is monitored according to the following criteria after each of the above messages sent: first time – presence of a response from the TM with the set attribute "Normal state" (NS) in the response word (RW); second time – "No response" condition; third time – presence of a response from the TM with the set NS attribute; the TM test is considered passed if the TM meets all three criteria, wherein after the messages generated and before they are sent to the TM, the signal containing the generated messages is converted into analogue form and amplified, then transmitted to the TM through a transformer.

EFFECT: expanded range of functional capabilities of testing due to the possibility of interaction with the tested devices using high voltage levels.

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