FIELD: data processing devices.
SUBSTANCE: device comprises external inputs of data ID and output of sums of deviations IUL, groups of external outputs of number of cycles QC, cycle parameters QB, deviations QS and sums of deviations QSA, first RS trigger of start-stop TSS 1, second delay trigger TZ 2, first AND element with inverse input 3, second AND element 4, first 5 and second 6 OR elements, first reversible bit counter CTB 7, NOR element 8, RF flag register 9, third trigger of the first bit of cycle TRB 10, second counter of number of cycles CTC 11, third counter of interval CTI 12, first 13 output buffer OB1, first 14 and second 15 DC decoders, groups of counters and second 20 output buffer OB2.
EFFECT: possibility of calculating cumulative sums, detecting and counting cycles of deviation of sums from zero, number of deviations by states in an input binary sequence.
1 cl, 3 dwg
