FIELD: computer technology.
SUBSTANCE: expected result is achieved due to the fact that the device contains an external data input DI, a group of external data outputs QB, a group of external outputs of the number of groups QG, the first RS start-stop trigger TSS 1, the first CTB 2 bit counter, the register of the number of the first bit of the RGB 3 group, the first element AND 4, the first element OR 5 with one inverse input, the second trigger of single bits TR1 6, the second element AND 7 with one inverse input, the second counter of units CTU 8, the block of equality of the lower boundary 9, the block of equality of the upper boundary 10, the third trigger of the lower boundary TRL 11, the fourth trigger of the upper limit of TRM 12, the third 13 and fourth 14 elements AND with two inverse inputs, the second element OR 15, the output buffer OB 16 and the third counter of the number of CTG groups 17, as well as the external inputs of asynchronous installation in the zero state of CLR are introduced, start device START, stop device STOP and clock S, external input buses of the lower limit GL and upper limit GM of the range of single bits, external exchange control bus EO, external flag “Buffer filled” FF and flag “Buffer empty” FZ.
EFFECT: possibility of identifying single groups of a given dimension, determining the number of groups and their location in the input data sequence.
1 cl, 4 dwg
