FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering, particularly to data processing devices. Device comprises an external data input, a group of external outputs of the number of cycles and cycle parameters, first RS-trigger of start-stop, second trigger of delay, AND element, OR element, first reversible bit counter, NOR element, flags register, third trigger of the first bit of the cycle, second counter of number of cycles, third interval counter and output buffer, as well as external inputs of clock signal, device start START and device stop STOP, internal bit counter zero state flag, cycle end flag and recording flag, external exchange control bus, external flag “Buffer full”, flag “Buffer empty”, flag “equality of zero and one bits” and flag “ones are more than zeros”.
EFFECT: providing the possibility of calculating cumulative sums, detecting and counting cycles of deviation of sums from zero, as well as determining the ratio between the number of unit and zero bits in the input sequence.
1 cl, 3 dwg
