FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering, particularly to microprocessors with parallel execution of several instructions. Processor has a preparatory pipeline, a register file, the first and second execution pipelines, an operand readiness control unit, an operand readiness register and a control unit. Preparatory conveyor is capable of separating the first and second personalized commands from the wide command. First and second execution conveyors are capable of synchronously with each other the first and second personalized instructions using the first and second groups of operands, respectively. Operand readiness control unit is capable of controlling the updating of the first group of operands in the register file. Operand readiness register is capable of storing a compromising flag when the first group of operands has not been updated before the execution of the first personalized instruction. In the presence of a compromising flag, the control unit is capable of recognizing the result of executing the first personalized command as an unreliable result.
EFFECT: high efficiency of the processor with simultaneous reduction of power consumption and the amount of heat released.
9 cl, 9 dwg
