PROCESSOR WITH INSTRUCTION LOADING IN CACHE LINE AND BRANCH PREDICTION Russian patent published in 2024 - IPC G06F9/34 G06F12/875 

FIELD: data processing.

SUBSTANCE: invention relates to processors with pipelined instruction processing. Processor comprises an instruction cache, a mask cache, a target address cache and a pipeline which includes a cache line buffer, a mask buffer and an instruction buffer; wherein the instruction memory is capable of storing instructions in the cache line and transmitting the cache line to the cache line buffer; mask memory is capable of storing a cache line mask for each cache line and transmitting it to the mask buffer when the instruction memory transmits the corresponding cache line to the cache line buffer; cache line mask comprises a sequence of bit values, where each bit value corresponds to its cache line instruction; cache line buffer based on the cache line mask stored in the mask buffer is capable of sequentially transmitting a cache line instruction to the instruction buffer, starting from the initial instruction and up to the first instruction with a given bit value; after transmitting a command with a given bit value, the cache line buffer is able to receive a called cache line from the command memory, which contains the called command, which becomes the initial instruction for the called cache line.

EFFECT: high efficiency of the processor and reduced power consumption.

2 cl, 4 dwg