FIELD: computer engineering.
SUBSTANCE: present technical solution relates to computer engineering. In the VLIW processor, the first and second preparatory pipelines are capable of processing in parallel to each other, respectively, the first and second sequences of wide instructions, wherein each wide instruction includes first and second personalized instructions to be executed by first and second execution pipelines, wherein the first execution conveyor is capable of executing a personalized instruction for preparing an initial transition starting a second preparation conveyor and preceding the personalized instruction for performing an initial transition, wherein the first and second execution pipelines are capable of receiving for execution the first and second personalized commands, selected from the wide commands of that one of the first and second sequences of wide commands, which is determined based on the result of the execution of the personalized instruction for the initial transition by the first or second execution pipeline.
EFFECT: shorter time spent by the VLIW processor on executing a program to increase speed and efficiency.
4 cl, 6 dwg
Title | Year | Author | Number |
---|---|---|---|
METHOD FOR PIPELINE PROCESSING OF INSTRUCTIONS FOR COMPUTER WITH VLIW PROCESSOR AND OPTIMIZING COMPILER AND COMPUTER FOR IMPLEMENTING METHOD | 2024 |
|
RU2820021C1 |
VLIW PROCESSOR WITH IMPROVED PERFORMANCE AT OPERAND UPDATE DELAY | 2023 |
|
RU2816092C1 |
CACHE PREDICTING METHOD AND DEVICE | 2012 |
|
RU2602335C2 |
ASYNCHRONOUS DATA PROCESSING DEVICE | 1997 |
|
RU2182353C2 |
COMPUTATIONAL MODULE FOR MULTI-STAGE MULTITHREADED PROCESSING OF DIGITAL DATA AND METHOD OF PROCESSING USING THIS MODULE | 2018 |
|
RU2681365C1 |
METHOD AND DEVICE FOR EXECUTING PROCESSOR INSTRUCTIONS BASED ON DYNAMICALLY VARIABLE DELAY | 2007 |
|
RU2419836C2 |
CACHING TARGET BRANCH ADDRESS WITH PREFETCHING | 2006 |
|
RU2358310C1 |
INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE | 2013 |
|
RU2662394C2 |
INSTRUCTION AND LOGIC FOR IDENTIFICATION OF INSTRUCTIONS FOR REMOVAL IN MULTI-FLOW PROCESSOR WITH SEQUENCE CHANGING | 2013 |
|
RU2644528C2 |
COMMAND AND LOGIC OF PROVIDING FUNCTIONAL CAPABILITIES OF CIPHER PROTECTED HASHING CYCLE | 2014 |
|
RU2637463C2 |
Authors
Dates
2024-03-26—Published
2024-01-18—Filed