FIELD: data processing.
SUBSTANCE: invention relates to microprocessors with pipelined instruction processing. Processor comprises a pipeline and a branch predictor, wherein the branch predictor is able to determine the result of executing the calling instruction to be loaded into the pipeline, and comprises actual and estimated saturating counters, each of which is capable of being in negative and positive initial and final states, wherein the actual counter is shifted towards the positive state when the result of executing the calling command is used to transition to the called command, and towards the negative state when the transition to the called command is not performed, and the estimated counter is capable of being shifted towards a positive state, or when the result of executing the calling instruction is a transition to the called instruction, and the previous state of the actual counter was positive, or when the result of executing the calling command is not to perform the transition to the called command, and the previous state of the actual counter was negative.
EFFECT: high efficiency and low power consumption of the processor.
3 cl, 5 dwg
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Authors
Dates
2024-12-24—Published
2024-05-18—Filed