FIELD: computer engineering.
SUBSTANCE: present technical solution relates to computer engineering. Device has an external N-bit input data bus ID of data units G, an external M-bit bus for setting the capacity of groups IU (where M≤N, K≤M), a group of external outputs of the number of groups in the QK unit, a group of external outputs of the initial digits of the groups in the QB unit, first group of (N-M+1)-th detection units 11, 12, …, 1(N-M+1), first groups 21, 22, …, 2M, from M OR elements with inverse input of the first group of detection units 11, 12, …, 1(N-M+1), second group of (M-1)-th detection units 31, 32, …, 3(M-1), second groups of I OR elements with inverse input 41, 42, …, 4(M-1) corresponding like I-th detection units of second group 31, 32, …, 3(M-1), (where I=1, … (M-1)), first group of (N-M+1)-th AND elements, 51, 52, …, 5(N-M+1), second group of (M-1)-th AND elements with inverse inputs 61, 62, …, 6(M-1), third group of (N-1)-th AND elements with inverse input 71, 73,…, 7N and unit counting units 8, as well as internal N-bit bus of initial digits of BB groups.
EFFECT: providing the possibility of detecting groups of single bits of a given capacity, determining the number of given groups and their arrangement in data units.
1 cl, 2 dwg
