FIELD: data processing devices.
SUBSTANCE: device contains an external data input ID for serial input of K-bit data blocks BB from the input N-bit binary data sequence, a group of external outputs of QB groups, a group of external outputs of maximum OH groups, a group of external buses of the number of unit groups Q1, Q2, …, Q(M+1) (where M is the bit depth of detected unit groups, 1≤ M≤ K), clock counter STS 1, counter of unit bits STV 2, decoder 3, inverter 4, output buffer of groups OB 5, group of (M+1) counters of unit groups 61, 62, …, 6(M+1), group of (M+1) adders 71, 72, …, 7(M+1), group of (M+1) registers 81, 82, …, 8(M+1), first element OR 9, group of (K-1) elements OR 101, 102, …, 10(K-1), a group of (K-1) AND elements with inverse input 111, 112, …, 11(K-1), second element OR 12, maximum group register RH 13, priority register RPR 14 and output buffer of maximum groups OH 15, as well as external input clock IC, synchronous setting to zero state IR and permission to operate ICE, internal buses for the number of single bits in the BD group, unitary code BDC, high group BS and BPR priority, internal flags for the beginning of the block F0, counting resolution FE and maximum FH, external buses for EO exchange control, external flags “Buffer full” FF and “Buffer empty” FZ.
EFFECT: expanding the scope of tools for the same purpose, in terms of the ability to detect groups of unit bits, determining the number of specified groups and identifying maximum groups in binary blocks, as well as counting unit groups in the input sequence.
1 cl, 2 dwg
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Authors
Dates
2023-12-15—Published
2023-08-07—Filed