FIELD: computer engineering.
SUBSTANCE: invention relates to the field of computing means, namely to microprocessors, and in particular to a device for controlling computing cores of an output accelerator of neural networks. Device for controlling computing devices of the neural network output accelerator, comprising on-chip the following elements: a parameter configuration unit connected to an external control device; segmented buffer memory connected to external memory; at least two instruction streams processing units, each of which is configured to: buffer the instruction stream received from the segmented buffer memory; decoding and synchronizing the stream of instructions; unit of descriptor indicators, made with possibility of receiving descriptor indicators from external control device; a unit for controlling requests for reading descriptors by pointers from the unit of descriptor pointers; an instruction set descriptor processing unit; instruction flow scheduler is configured to load a set of instructions and control the fullness of segments of said memory.
EFFECT: high efficiency of the accelerator due to reduced idle time of computational cores.
14 cl, 4 dwg
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Authors
Dates
2024-12-24—Published
2024-09-26—Filed