FIELD: physics.
SUBSTANCE: invention relates to low-density parity-check decoding. Decoder uses a partially parallel architecture with complete overlapping of check and variable node blocks, which allows them to operate independently of each other, and the memory blocks organization based on the shift registers provides the data breaking down into vectors and ensures their storage in the form of an array in accordance with the submatrix size in the order of rows (columns) without address conflicts, which provides high throughput during decoding and reduces data transmission delay time without deterioration of other parameters of the decoder.
EFFECT: fewer hardware resources and reduced read/write delay when organizing memory and optimizing power consumption.
1 cl, 4 dwg
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