FIELD: computer engineering, in particular, read-only memory units which are cleared and programmed electrically. SUBSTANCE: device has network of memory nodes. Said network is designed as matrix of serial circuits of NAND gates. Each memory node is made from superposition of charge accumulation layer and control gate over semiconductor substrate. Electric clearing is achieved by mutual charge exchange between charge accumulation layer and substrate. In addition device has data lock circuit LT, high-voltage source HV, power supply CS, program control circuit PC and program state detection circuit PS. In addition device has page buffer memory PB for memory unit which is cleared and programmed electrically. Page buffer unit provides possibility of paging mode. EFFECT: increased functional capabilities. 3 cl, 7 dwg
