FIELD: microelectronics. SUBSTANCE: large-scale integrated-circuit structure has semiconductor substrate with n- and p-regions for p- and n-channel transistors, respectively, incorporating functional areas with source and drain regions of p- and n-channel transistors, gates of p- and n-channel transistors, their contacts for connecting to high- and low-potential buses, respectively, contact pads made in gate switching areas separating source and drain regions of p- and n-channel transistors, areas of resistive contacts for n- and p-regions of substrate, and high- and low-potential buses. Contact pads in gate switching areas are common for four nearest gates for connection to any of four closest gates of two p-channel transistors and two n-channel transistors. Contacts for source and drain regions of p- and n-channel transistors are made in locating areas of high- and low-potential buses, respectively, just under buses proper. Contacts for gates of p- and n-channel transistors are made in locating areas of high- and low-potential buses, respectively, directly under them so as to isolate structure. Areas of resistive contacts for n- and p-regions of substrate are made in locating areas of high- and low-potential buses, respectively, directly under them. EFFECT: improved efficiency of chip area utilization. 4 cl, 11 dwg
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Authors
Dates
1997-07-20—Published
1992-09-10—Filed