RANDOM-ACCESS MEMORY CELL Russian patent published in 2024 - IPC H10B12/00 B82Y40/00 

FIELD: semiconductor devices.

SUBSTANCE: random access memory (RAM) memory cell contains an n-channel MOS transistor made on a substrate, and a charging capacitor, connected to the RAM discharge, address and reading buses, wherein said n-channel MOS transistor is in form of a multi-channel n-type of conductivity MOS transistor on an i-GaAs insulating substrate; in said i-GaAs insulating substrate there is a source n⁺-type of conductivity epitaxial hetero-region based on AlGaAs or InGaP, epitaxial high-resistance n^--type of conductivity GaAs layer and heterolayer of drain based on AlGaAs or InGaP of n⁺-type of conductivity; wherein on the surface of the source n⁺-type of conductivity of the epitaxial hetero-region there is an n⁺-type of conductivity GaAs nanolayer, on which there is an ohmic contact connected to the discharge line; on the surface of said drain heterolayer there are n⁺-type of conductivity epitaxial nanolayer of GaAs, an ohmic contact, a platinum Pt nanolayer, an atomic-layer dielectric layer of a dielectric of a charging capacitance with a high dielectric constant, series-deposited nanolayer of platinum Pt and ohmic contact connected to address bus; on the surface of the above epitaxial high-resistance layer there is a subgate dielectric nanolayer and an ohmic contact connected to the readout bus.

EFFECT: increased electrical strength of the RAM cell with the nanosize of the MOS transistor; increase of specific dielectric permeability of dielectric with design of charging capacitance; reduction of parasitic charge leakages in order to reduce charge regeneration cycles; reduction of random access time during reading; increased density of cells in single system RAM on one chip; high operating temperature of RAM cells and the system as a whole and high efficiency of the RAM memory cell.

1 cl, 6 dwg