PAGE ERASING MODE IN FLASH-MEMORY ARRAY Russian patent published in 2004 - IPC

FIELD: erasing mode in flash-memory array. SUBSTANCE: flash-memory array device has plurality of memory location transistors; means for feeding first voltage to control gate of at least one erasable memory location transistor; means for feeding second voltage more positive than first one to control gates of all transistors of mentioned memory locations other than at least one transistor of mentioned erasable memory location; means for feeding third voltage more positive than mentioned second one to drain of at least one mentioned transistor of mentioned erasable memory location and to drains of mentioned transistors of non-erasable memory locations. Operating process of mentioned device is given in description of invention. EFFECT: greatly reduced excitation at memory locations not chosen for erasing in erasing chosen ones. 14 cl, 4 dwg