FIELD: computer engineering, in particular, large integral circuits. SUBSTANCE: device has semiconductor substrate of first conductance type, semiconductor substrate of second conductance type, thin dielectric layers, power supply region, zero potential region, two input regions, transistor of second conductance type, input polysilicon S-shaped line, output S-shaped region. Transit region has transit polysilicon line which is shaped as mirrored S. Input, output and transit regions have equal size. Projection borders of input regions, transit region, regions of power supply and zero potential are crossed by contact windows. EFFECT: decreased size, increased speed. 1 dwg, 1 tbl
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Authors
Dates
1998-07-20—Published
1996-04-23—Filed