INTEGRATED-CIRCUIT AND-OR-NOT GATE Russian patent published in 2001 - IPC

FIELD: computer engineering and integrated electronics; large-scale integrated-circuit gates. SUBSTANCE: integrated-circuit gate built around complementary normally closed field-effect transistors with Schottky barrier controlled junctions has drain, source, and channel regions of four transistors of second polarity of conductivity, metal gates of Schottky barrier transistors of second polarity of conductivity, four input metal buses connected to gates of transistors of second polarity of conductivity, output metal bus connected to drain regions of fist and second transistors of second polarity of conductivity, insulating layer, zero-potential metal bus, and metal power bus; newly introduced in device are semiconductor substrate of second polarity of conductivity that functions as common source region for second and fourth transistors of second polarity of conductivity and is connected over its entire free surface to zero-potential metal bus, drain, source, and channel regions of four transistors of first polarity of conductivity, metal Schottky barrier gates of transistors of first polarity of conductivity connected to input metal buses, metal bus connected to regions of first polarity of conductivity that function as sources of sixth and eighth transistors of first polarity of conductivity and as drains of fifth and seventh ones, semiconductor substrate of first polarity of conductivity that functions as common source region for fifth and seventh transistors of first polarity of conductivity and is connected over its entire length to metal power bus; transistors are made in the form of two prisms with square bases area of each base equals that of one contact cut; each prism has two transistors of second polarity of conductivity and two transistors of first polarity of conductivity mounted one on top of other with their channels positioned vertically; metal Schottky barrier gates are ring-shaped; transistor channel length depends on thickness of metal gate; metal buses are placed in nine layers separated by insulating layers; input metal buses are placed in same layers as semiconductor regions of transistors. EFFECT: reduced space requirement, enhanced speed, reduced input and change-over power. 1 cl, 4 dwg