CIRCUIT ARRANGEMENT FOR REDUCING DELAY IN TRANSMITTING BUFFER DATA BETWEEN TWO ONE-TO-ONE ASYNCHRONOUS BUSES Russian patent published in 2001 - IPC

Abstract RU 2176814 C2

FIELD: computer systems; digital subsystems controlling data transmission between two synchronous buses. SUBSTANCE: first-to-second bus interface incorporates end circuit breaker of first bus that functions to control data transmission from first data bus to data buffer and end circuit breaker of second bus used to control data transmission from data buffer to second data bus. Respective valid-data flag is set for each storage location by end circuit breaker of first-bus interface when data are stored in storage location for data coming from first bus and cleared by end circuit breaker of second-bus interface when data are transmitted from storage location to second bus. For reducing time required for output of serial data from set of data storage locations in data buffer each data validity flag is synchronized independently. EFFECT: enhanced capacity of computer system. 5 cl, 5 dwg

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RU 2 176 814 C2

Authors

Mout Randall

Dates

2001-12-10Published

1996-06-06Filed