FIELD: electronics, in particular, binary adders. SUBSTANCE: goal of invention is achieved by design of first to (n-1) carry detection signal generators, which execute function of the type AB(C+D)+CD+EF. First to (n-2) carry transmission signal generators are designed as 2OR-2OR-2OR-3AND gates. (n-1) carry transmission signal generators is designed as is designed using 2OR-2OR-2AND gate. Inputs of each pair of OR junctions of carry transmission signal generators are connected to inputs of pair bits of added numbers in ascending order starting from next number after two lowermost bits. This results in possibility to increase circuit bit length without increase in number of circuits in critical carry signal transmission path, leading to decreased speed of device operations. EFFECT: increased bit length, increased speed. 3 cl, 4 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| RAPID CARRY CIRCUIT | 1999 |
|
RU2149443C1 |
| HIGH-SPEED CARRY ADDING DEVICE | 2000 |
|
RU2198421C2 |
| GENERATOR OF WRITE PULSES FOR MEMORY UNIT | 1994 |
|
RU2097843C1 |
| MEMORY UNIT | 1995 |
|
RU2101785C1 |
| MULTIBIT CONTROLLED FREQUENCY SCALER | 1996 |
|
RU2119248C1 |
| DURATION-TO-CODE CONVERTER | 2001 |
|
RU2210097C2 |
| BASE MATRIX CRYSTAL OF ON-LINE STORAGE | 1992 |
|
RU2089012C1 |
| MULTICHANNEL TELEMETRIC SEISMIC PROSPECTING SYSTEM | 1994 |
|
RU2107312C1 |
| CMOS GATE LEVEL CONVERTER | 1994 |
|
RU2097914C1 |
| STANDARD VOLTAGE SOURCE | 1993 |
|
RU2076351C1 |
