FIELD: digital computer engineering. SUBSTANCE: memory cell has first transistor inverter with first input and first output, as well as second inverter with second input and second output. First and second transistors are coupled with first and second cross connectors. First cross connector interconnects first input and second output. Second cross connector interconnects second input and first output. In the course of manufacture of superconductor two cross connectors have different conducting layers. Crosses are made in different materials and on different layers of device. That is why, crosses can be arranged vertically one above other thereby reducing memory cell surface area. EFFECT: reduced cost and improved reliability of cell. 25 cl, 8 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| DARK-CURRENT REDUCING RING | 1998 |
|
RU2178600C1 |
| METHOD FOR MANUFACTURING OF MOS MEMORY REGISTER, MEMORY REGISTER AND MATRIX MEMORY UNIT WHICH USES THIS REGISTER | 1996 |
|
RU2105383C1 |
| MATRIX STORAGE FOR READ-ONLY MEMORY | 0 |
|
SU1444890A1 |
| MATRIX STORAGE FOR READ-ONLY MEMORY | 0 |
|
SU1444891A1 |
| TECHNOLOGY OF CREATING CONNECTIONS THROUGH MATRIX OF MEMORY CELLS IN NONVOLATILE MEMORY DEVICE | 2015 |
|
RU2661992C2 |
| CONSERVATION OF RE-DISTRIBUTING THE CONDUCTIVE PATHS, WHICH HAVE A SMALL STEP | 2013 |
|
RU2631911C2 |
| DYNAMIC MEMORY LOCATION | 1990 |
|
RU2029393C1 |
| CELL OF NONVOLATILE ELECTRICALLY PROGRAMMABLE MEMORY | 2010 |
|
RU2436190C1 |
| SEMICONDUCTOR MEMORY DEVICE | 2014 |
|
RU2642960C2 |
| METHODS OF FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS | 2009 |
|
RU2492554C2 |
