FIELD: microelectronics. SUBSTANCE: storage cell has only one MOS transistor formed by source-channel-drain junction with its semiconductor substrate 1 of first polarity of conductivity carrying drain region 2 and source region 3 of second polarity of conductivity; electrode of gate 4 electrically insulated from drain region 2 by tunnel oxide and from channel region 9 located between drain and source regions 2 and 3 by oxide of gate 5,10 is placed at variable potential; it stretches towards source-channel- drain junction at least above part of channel region 9 and part of drain region 2; control electrode 7 is electrically insulated from electrode of gate 4 by coupling oxide 8. For programming the storage cell, high negative voltage is applied to control electrode 7, supply voltage, to drain electrode D, and zero potential, to electrode of source 5. For erasing the storage cell, high positive voltage is applied to control electrode 7 and to source electrode S while drain electrode D is disconnected. EFFECT: reduced absolute value of high voltages that enables reduction of hardware manufacturing cost. 8 cl, 4 dwg
